Design Implementation of High-Performance Pipelined ADC

Authors

  • Dr. Priyesh P. Gandhi  General Manager, Prakruti Consultancy Services, Vadodara, Gujarat, India

Keywords:

Analog to Digital Converters (ADCs), Propagation delay, Offset Voltage, Power Dissipation, Comparator, Operational Amplifier (OP-AMP)

Abstract

This paper presents Design Implementation of High-Performance ADC in Deep-Submicron Technology. The Analog-to-Digital Converter (ADC) is the main link between the analog input and DSP part. However, for applications like hand-held or wireless devices, ADC should be featured with low power and high speed. The pipeline ADC architecture is best suitable for medium resolution, low power and high-speed applications. For design point of it is very flexible for power and area constraints. Main building-blocks in each stage of the pipelined ADC are sample and hold, sub-ADC, sub DAC and amplifier. First few implementations for each sub-block were reviewed. Then by selecting appropriate blocks 8-Bit pipelined ADC with sampling frequency 100 MHz is designed using CMOS TSMC 0.18 μm technology. The design has 1-Bit stage resolution. The power dissipation of the implemented ADC is found less than 82mW. Second Design shows the 1-Bit resolution with a power dissipation of 56 mW. By few modifications in design, effect of stage resolution and effect of other amplifier topology on power is observed. The analysis is very useful to decide the stage resolution. This power analysis is supported by suitable simulation results.

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2019-02-25

Issue

Volume 6, Issue 1, January-February-2019

Section

Research Articles

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How to Cite

[1]
Dr. Priyesh P. Gandhi, " Design Implementation of High-Performance Pipelined ADC, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 6, Issue 1, pp.526-536, January-February-2019.