RTL Design, Verification and Synthesis of Secure Hash Algorithm to implement on an ASIC Processor

Authors(5) :-Akhilesh S Narayan, Ashish J, Noor Afreen, Lithesh V S, Sandeep R

In this project we are comparing different architectures and adding the features that increases the efficiency of our architecture. Few of them are including multiplexers in the message digester, using different adder architectures in the required places, reducing the critical path by breaking the longest path and making them to operate parallelly. Use of multiplexers reduces the number of registers required in the message expander. It simply transfers the output of expander to compressor block in every clock cycle. Whenever the number of cycle is greater than 16, the multiplexer switches the select line so that the computed message digest to send as output to the compressor. Using of a carry save adder and adder array takes lesser time to perform addition than a pair of adders array. Finally we all know that reducing the critical path reduces the overall operation time and hence increases the efficiency. Considering all these factors in the design we are designing the microarchitecture for SHA-256 algorithm and obtain the RTL code for that architecture. We have also verified the design by designing a test-bench, and finally synthesized the design.

Authors and Affiliations

Akhilesh S Narayan
Department of ECE, VVCE, Mysore, Karnataka, India
Ashish J
Department of ECE, VVCE, Mysore, Karnataka, India
Noor Afreen
Department of ECE, VVCE, Mysore, Karnataka, India
Lithesh V S
Department of ECE, VVCE, Mysore, Karnataka, India
Sandeep R
Associate Professor, Department of ECE, VVCE, Mysore, Karnataka, India

SHA 256, Bit Coin, Block chain, Microarchitecture, RTL

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Publication Details

Published in : Volume 6 | Issue 3 | May-June 2019
Date of Publication : 2019-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 70-75
Manuscript Number : IJSRSET196318
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Akhilesh S Narayan, Ashish J, Noor Afreen, Lithesh V S, Sandeep R, " RTL Design, Verification and Synthesis of Secure Hash Algorithm to implement on an ASIC Processor, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 6, Issue 3, pp.70-75, May-June-2019. Available at doi : https://doi.org/10.32628/IJSRSET196318
Journal URL : http://ijsrset.com/IJSRSET196318

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