Embedded System Design Processor using GAA
Keywords:
Processor, Hardware Description Language, bluespec, Pipeline, Register Files, RISC V, Instruction Set Architecture.Abstract
Electronics system design is the evolutionary task which is concentrating on the system design for various things like processor, SoC for real time system, embedded systems, reconfigurable system design and more where the Processor design is one of them; it may be a single core, or more than one cores depends on the requirement Specification. There are various hardware description languages used to design and fabricate the processor, among them Verilog, VHDL, SystemVerilog and Bluespec System Verilog are few of them. Bluespec is the one of the modern hardware synthesizable language with guarded atomic action(GAA), which has many advantages over the others. This paper presents the design and implementation of pipeline based 64-bit processor using bluespec, also presents the analysis of number of clock cycles per instructions, implementation of RISC V instruction sets and working principle of pipeline processor using bluespec.
References
- http://www.bluespec.com/technology.html
- Tariquzzaman , Syed Rizwan Ali , Nahid Kausar FPGA implementation of 64 bit RISC processor with Vedic multiplier using VHDL, IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-ISSN: 2278-1676, p-ISSN: 2320-3331 PP 12-16
- Manju Rani Harpreet Vohra Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA International Journal of Electronics Communication and Computer Technology (IJECCT) Volume 2 Issue 4 (July 2012)
- Kirat Pal Singh and Shivani Parmar ”Vhdl Implementation of a MIPS – 32 Pipeline Processor” International Journal of Applied Engineering Research, ISSN 0973 – 4562 vol. 7 No. 11. 2012
- Shankar Kumar Mishra, Dr. Nisha P Sarware “Review of 5 stage Pipelined Architecture of 8 Bit Pico Processor”, International Journal of Electronics, Communication & Soft Computing Science and Engineering, ISSN: 2277-9477, Volume 3, Issue 4
- Navneet kaur , Adesh Kumar , Lipika Gupta VHDL Design and Synthesis of 64 bit RISC Processor System on IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 3, Issue 5 (Nov. – Dec. 2013)
- Rishiyur S. Nikhil and Kathy Czeck BSV by Example, The next-generation language for electronic system design Revision: November 3, 2010
- Arvind et al,Computer Architecture: A Constructive Approach Using Executable and Synthesizable Speci_cations 2012-2013
- Rakesh M.R ,RISC Processor Design in VLSI Technology Using the Pipeline Technique, INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING Vol. 2, Issue4, April 2014.
- Navneet kaur , Adesh Kumar , Lipika Gupta VHDL Design and Synthesis of 64 bit RISC Processor System on Chip (SoC) IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 3, Issue 5 (Nov. – Dec. 2013)
- Imran Mohammad , Ramananjaneyulu K, FPGA Implementation of a 64-Bit RISC Processor Using VHDL International Journal of Reconfigurable and Embedded Systems (IJRES) Vol. 1, No. 2, July 2012
- P. Devi Pradeep and D.Srinivasa Rao Design and Implementation of 64-Bit RISC Processor for Industry Automation International Journal of u- and e- Service, Science and Technology Vol.8, No.1 (2015), pp.427-434
- Nirav Dave, Designing a Reorder Buffer in Bluespec 0-7803-8509-8/041$20.00 8 2004 IEEE.
- Rishiyur S et al, BSV by Example The next-generation language for electronic system design Revision: November 3, 2010
- Arvind et al, Computer Architecture: A Constructive Approach Using Executable and Synthesizable Specifications December 31, 2012
- http://cse-wiki.unl.edu/wiki/index.php/CSE430/830-2011SpringTeamB
- Andrew Waterman et al, The RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.0 May 6, 2014
Downloads
Published
Issue
Section
License
Copyright (c) IJSRSET
This work is licensed under a Creative Commons Attribution 4.0 International License.