Study of Jtag-Tap Controller for Board Level Testing

Authors

  • V. Jayapradha  Assistant Professor Department of Electronics and Communication Engineering SCSVMV, Tamil Nadu, India

Keywords:

Abstract

This paper gives the detailed study of Test Access Port (TAP) and its functions associated with boundary scan testing for various Unit under Test (UUT).It also explain the boundary scan instructions and the signals through the TAP controller. Supports the applications of testing the devices on various factor using JTAG standard.

References

  1. IEEE. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE, 1993.
  2. IEEE Std 1149.1-2001, "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE, USA, 2001.
  3. Dilip Bhavsar," Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability", IEEE Design & Test of Computers,2000.
  4. Heiko Ehrenberg, White Paper: Design-For- Testability Guidelines for Boundary Scan Test, GOEPEL Electronics, 2004

International Journal of Scientific Research in Science, Engineering and Technology

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Published

2018-03-23

Issue

Volume 5, Issue 1, March-April-2018

Section

Research Articles

License

Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
V. Jayapradha, " Study of Jtag-Tap Controller for Board Level Testing, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 5, Issue 1, pp.81-83, March-April-2018.