Network - On - Chip Router Microarchitecture for Future Communication : A Comprehensive Review

Authors

  • Ramanamma Parepalli  Assistant Professor, Electronics and Communication Department, New Horizon college of Engineering , Bangalore, Karnataka, India
  • Dr. B Mohan Kumar Naik  Professor, Electronics and Communication Department, New Horizon college of Engineering , Bangalore, Karnataka, India

Keywords:

NoC router, VC allocator, Switch allocator, Switch traversal.

Abstract

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). NoC architecture is a preferable communication backbone for today’s multiprocessor platforms. NoCs utilize routers at each node to direct traffic. However, designing a high performance, low latency NoC with low area overhead has remained a challenge. Conventional NoC router micro-architecture has main drawbacks in terms of circuit complexity, high critical path delay, resource utilization, timing, and power efficiency. The growing reliance on intellectual properties exposes SoCs to many security vulnerabilities and is raising more and more concerns. At the same time, with the quick increase in chip density and deep scaling of feature size, current billion-transistor chip designs introduce more challenges to manufacturing fault-free chips. The research presented in this paper has investigated these issues in detail and wants to develop a low latency, low-power and high-performance NoC router architecture that is applicable to a wide range of FPGA families.

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Published

2021-03-27

Issue

Section

Research Articles

How to Cite

[1]
Ramanamma Parepalli, Dr. B Mohan Kumar Naik "Network - On - Chip Router Microarchitecture for Future Communication : A Comprehensive Review" International Journal of Scientific Research in Science, Engineering and Technology (IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 9, Issue 1, pp.223-229, March-April-2021.