Design of Delay Lock Loop with Dual Control Using LT-Spice
Keywords:
CMOS, time-of-flight, delay-locked loop, Positron emission tomography, CDR, VCDL, LPFAbstract
The paper presents “A CMOS Delay Lock Loop with Dual Control”. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A precise multiphase clock generator should be required. Generally, the timing generator is realized by using a delay-locked loop (DLL) due to its good performances on low jitter and easier integration implemented in CMOS process.
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