Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits

Authors

  • Niranjan Kumar  Department of Electronics and Communication Engineering, Trinity Institute of Technology and Research Bhopal, Madhyapradesh, India
  • Vipul Aggarwal  Department of Electronics and Communication Engineering, Trinity Institute of Technology and Research Bhopal, Madhyapradesh, India

Keywords:

CMOS, Adders, VLSI Design, CAD, process technology, delay analysis

Abstract

In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically implemented using basic logic gates namely XOR and AND gates. Half Adders or Full adders may be realized in various ways depending on the various process technologies and design methodologies deployed for making these digital integrated circuits design. The Full adder, 14T, pseudo-nMOS, MULTIPLEXER-BASED FULL ADDER , 8T, Inverter-based full-adder with pass transistors, Conventional CMOS (C-CMOS), 20T,10Twith 4T-XNOR, 6T, 16T, 9T, Double gate MOSFET and hybrid 1-bit full adder full adders etc

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2016-06-30

Issue

Volume 2, Issue 3, May-June-2016

Section

Research Articles

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How to Cite

[1]
Niranjan Kumar, Vipul Aggarwal "Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits" International Journal of Scientific Research in Science, Engineering and Technology (IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.449-453, May-June-2016.