Design and Performance Investigation of Binary Signed Digit Adder

Authors

  • Sharmila Hemanandh  ECE, JEPPIAAR SRR Engineering College , Chennai, Tamil Nadu, India
  • Aishwarya Gopinath   ECE, JEPPIAAR SRR Engineering College , Chennai, Tamil Nadu, India
  • S. Karthika  ECE, JEPPIAAR SRR Engineering College , Chennai, Tamil Nadu, India
  • B. Nandhini  ECE, JEPPIAAR SRR Engineering College , Chennai, Tamil Nadu, India

Keywords:

Fast Adders, CSA, CLA, BSD

Abstract

An Adder is a basic building block of a digital system. In general, an adder is a digital circuit that performs addition of numbers. Adders play a vital role in deciding the overall performance of digital signal processing applications. They are also utilized in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators etc. The type of number representation used in the design of adders influence the performance of the adder and hence the digital system. This paper proposes the design of Binary Signed Digit (BSD) adder based on signed digit number representation. Binary Signed Digit representation results in fast and propagation free addition. The carry free addition offers many advantages in the implementation of arithmetic circuits. The advantages and disadvantages of Fast adders such as Carry Save Adder (CSA) and Carry Look Ahead Adder (CLA) are studied. The adders are discussed and the performance parameters such as area and power are compared. The adders are designed using Xilinx and implemented with XC9572XL-5-TQ100.The results prove that the proposed Binary Signed Digit adder is highly efficient than the other two fast adders.

References

  1. L.Wanhammer, (1999). "DSP Integrated Circuits,” Academic Press, ISSN No.
  2. J.Melander, (1997) "Design of SIC FFT Architectures,” Linkoping Studies in Science and Technology, Thesis No.618, Linkoping University, Sweden.
  3. K.K.Parhi, (2001), "VLSI Digital Signal Processing Systems: Design and Implementation,” John Wiley & Sons..
  4. S. Knowles, (2001) "A family of adders,” Proceeding of 15th Symp. Computer Arithmetic, pp. 277–281. 
  5. J. Park, H. C. Ngo, J. A. Silberman, and S. H. Dong, (2000) , "470 ps 64 bit parallel binary adder,” Symp. VLSI Circuits, pp. 192–193.
  6. Ning Zhu; Wang-Ling Goh; Kiat-Seng Yeo, (2009). "An enhanced low-power high-speed Adder For Error-Tolerant application," Integrated Circuits, ISIC '09. Proceedings of the 12th International Symposium.  pp. 69-72.
  7. G.Wang, M.Ozaydin, and M.Tull, (2002). "High-Performance Divider Using Redundant Binary Representation," in Proc. 45th Midwest Symp. On Circuits andSystems,Vol.1, Aug.2002, pp.471-474.
  8. Kharbash, F. Chaudhry, G. M., "Binary Signed Digit Number Adder Design with Error Detection Capability," Sharjah 9th International Symposium on signal processing and Its Applications, ISSPA, pp.1-4,
  9. A.Avizenis, "Signed-Digit Number Representations for Fast Parallel Arithmetic 1961, " IRE Trans. On Electronic Computers,   pp.389-400.
  10. Y.Harata, Y.Nakamura, H.Nagase, M.Takigawa, and N.Takagi, (1987) "A High Speed Multiplier Using a Redandant Binary Adder Tree," IEEE J. of Solid-State Circuits, Vol. 22, no. 1, pp. 28-31.

International Journal of Scientific Research in Science, Engineering and Technology

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Published

2017-04-30

Issue

Volume 3, Issue 2, March-April-2017

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Sharmila Hemanandh, Aishwarya Gopinath , S. Karthika, B. Nandhini "Design and Performance Investigation of Binary Signed Digit Adder" International Journal of Scientific Research in Science, Engineering and Technology (IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 2, pp.327-331, March-April-2017.