Design of Radix-8 Mbe-Multiplier Based on Efficient Parallel Multiplier Accumulator

Abstract

The parallel multiplier-accumulator based radix-8 modified booth recorder is a very promising and emerging multiplication technology because of its various benefits like high density thanks to less no of execution blocks, low power dissipation and nice performance speed. During this projected project an innovative design of multiplier-and-accumulator (MAC) is employed for top speed and low-power style and it's achieved by mistreatment the renewed adder and modified booth encoder technique. This recommended multiplier 16-bit modified booth encoder design fortified with SPST adder is controlled by a general AND logic data detection unit. This booth modified algorithm encoder will persistently reduce the generating partial-products logic blocks by a number factor of 2. This novel designed SPST hybrid carry save adder (CSA) saves the generated carry and so parallel multiplication is done without waiting for carry from LSB carry, it reduce the quantity of bits in the last adder which will avoids the excessive addition and consequently minimize the switch power dissipation, and conjointly thanks to an occasional low power fitted with performance enhanced carry select adder (CSA) logic circuit. The front end design VLSI tool Xilinx-ISE v14 simulator is used for logical verification, and Xilinx-ISE v14 tool for further synthesizing and performing placing execution blocks & wire routing operation for system verification on targeted FPGA. This proposed multiplier time taken to execute 2x16-bit multiplication operation and time to produce 32-bit output is typically high speeder then all existing designs.