Design of Single Precision Floating Point Multiplication Algorithm with Vector Support

Authors

  • T.GOVINDARAO  Research Scholar, Department of ECE, GMRIT, RAJAM, AP, INDIA
  • D.ARUN KUMAR  Department of ECE, GMRIT, RAJAM, AP, INDIA

Keywords:

Floating point multiplier, GPUS, operating frequency, HDL

Abstract

This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications. The floating point units consume less power and small part of total area. Graphic Processor Units (GPUS) are specially tuned for performing a set of operations on large sets of data. This paper work presents the design of a single precision floating point multiplication algorithm with vector support. The single precision floating point multiplier is having a path delay of 72ns and also having the operating frequency of 13.58MHz.Finally this implementation is done in Verilog HDL using Xilinx ISE-14.2.

References

 [1] Alok Baluni,Farhad Merchant ,s.k.nandy,s.Balakrishnan,”a Fully Pipelined Modular Multiple Precision Floating Point Multiplier With Vector Support” 2011 international symposium on Electronic system design(ISED)PP.45-50.

[2] IEEE,IEEE Standard for Binary Floating-Point Arithmetic.IEEE.1985.

[3] K.Manopolous,D.Reises,V.A.Chouiaras “An Efficient Multiple Precision Floating Point Multiplier”2011 IEEE.PP 153-156.

[4] E.Stenersen,”Vectorized 256-bit input fp16/fp32/fp64 floating point multiplier ” Norwegain University of Science and Technology,2007.

[5] I. Koren, Computer Arithmetic Algorithms. Natick, MA, USA: A. K.Peters, Ltd.,                               2001.

[6] S. T. Oskuli, Design of Low-Power Reduction-Trees in Parallel multipliers PhD thesis,  Norwegian University of Science and Technology,2008.

[7] G. Even and P.-M. Seidel, “A comparison of three rounding algorithms for IEEE floating-point multiplication,” IEEE Trans. Comput., vol. 49, no. 7, pp. 638–650,                    

[8] N. T. Quach , N. Takagi, and M. J. Flynn, “Systematic IEEE rounding method for high                            

    Speed floating-point multipliers,” IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 5, pp. 511–521, 2004.         

[9] L. Wanhammar, DSP Integrated Circuits. Academic Press, 1999.


International Journal of Scientific Research in Science, Engineering and Technology

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Published

2015-02-25

Issue

Volume 1, Issue 1, January-February-2015

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
T.GOVINDARAO, D.ARUN KUMAR, " Design of Single Precision Floating Point Multiplication Algorithm with Vector Support, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 1, pp.62-69, January-February-2015.