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Design of Single Precision Floating Point Multiplication Algorithm with Vector Support


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This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications. The floating point units consume less power and small part of total area. Graphic Processor Units (GPUS) are specially tuned for performing a set of operations on large sets of data. This paper work presents the design of a single precision floating point multiplication algorithm with vector support. The single precision floating point multiplier is having a path delay of 72ns and also having the operating frequency of 13.58MHz.Finally this implementation is done in Verilog HDL using Xilinx ISE-14.2.


Floating point multiplier, GPUS, operating frequency, HDL


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Publication Details

Published in : Volume 1 | Issue 1 | January-Febuary - 2015
Date of Publication Print ISSN Online ISSN
2015-02-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
62-69 IJSRSET15113   Technoscience Academy

Cite This Article

T.GOVINDARAO, D.ARUN KUMAR, "Design of Single Precision Floating Point Multiplication Algorithm with Vector Support", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 1, pp.62-69, January-Febuary-2015.
URL : http://ijsrset.com/IJSRSET15113.php