Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA

Authors(2) :-G. Naresh, P. Praveenkumar

Self-checking carry-select adder design based on two-rail encoding is an efficient method, due to its arithmetic operations and short delay. This paper presents the design of the Compressor based Self-checking carry-select adder design .The circuit can detect all single stuck-at faults during on-line operation mode. Its performance is increased by using compressor by replacing all full adders.

Authors and Affiliations

G. Naresh
Department of Electrical Communication Engineering K. M. M Institute of Technology and Science, Tirupati, Chittoor, Andhra Pradesh, India
P. Praveenkumar
Department of Electrical Communication Engineering K. M. M Institute of Technology and Science, Tirupati, Chittoor, Andhra Pradesh, India

Compressor, carry select Adder, Area, Delay, Area-Delay Product.

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Publication Details

Published in : Volume 1 | Issue 4 | July-August 2015
Date of Publication : 2015-08-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 412-414
Manuscript Number : IJSRSET151480
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

G. Naresh, P. Praveenkumar, " Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 4, pp.412-414, July-August-2015.
Journal URL : http://ijsrset.com/IJSRSET151480

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