AMBA-APB RTL Implementation Using Efficient Resources and Constructs through Verilog

Abstract

The challenge in engineering VLSI based IC design to find an optimum solution for chip which will satisfy the needs of Power, area and efficiency. The aim of this paper is to design and AMBA-APB RTL which is highly efficient in power and size issues. The reusability of design and easy configurability are the focus area of this paper through which design will be implemented. The Design specification is based on ARM based AMBA_APB specification version V2.0. For the simulation task, ModelSim Version 10.3 has been used. For the synthesisation purpose, design utilization summary and power details Xilinx-ISE design software has been used. Power report is introduced for developing better and clear understanding of the power utilization and distribution in any system. The power report gives the power consumption summary.The total clocks power consumption in chip is of 0.38mW, total hierarchy power consumption of 0.52 mW and total on chip logical power consumption of 0.111 W have been extracted from Xilinx XPower analyser tool when APB Bridge is designed under the proposed design approach.