Analog Multiplier Based on Squarer Cells

Authors(2) :-Reza Zarei, Moora Maali

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

Authors and Affiliations

Reza Zarei
Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Tehran, Iran
Moora Maali
University of Kurdistan, Sanandaj, Kurdistan, Iran

Analog Multiplier, Squarer Cell.

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Publication Details

Published in : Volume 4 | Issue 10 | September-October 2018
Date of Publication : 2018-10-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 350-354
Manuscript Number : IJSRSET1841078
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Reza Zarei, Moora Maali, " Analog Multiplier Based on Squarer Cells, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 10, pp.350-354, September-October-2018. Available at doi : https://doi.org/10.32628IJSRSET1841078
Journal URL : http://ijsrset.com/IJSRSET1841078

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