Design and Simulation of Advance Multi Precision Arithmetic Adder Using VHDL

Abstract

In the design of digital circuits using programmable logic array such as FPGA/CPLD low propagation delay, high speed & low area are the major parameter to be achieved. Digital circuits’ especially digital adders are implemented through three methods Ripple carry adder, Carry look-ahead adder and Carry select adder. Ripple carry adder suffers from high area and high propagation delay and high speed. Carry select adder incorporates pair of adder and select desired output sum and carry through multiplexers. Therefore carry look ahead adder suffers from high area requirements but achieving high speed of operations. Design of homogeneous single precision adder includes either ripple carry adder or carry look-ahead adder in combination with carry select adder in combines the advantages and disadvantages of both adders. It is proposed to design hybrid multi precision adder that includes Ripple carry adder, Carry look-ahead adder and Carry select adder. Hybrid adders combine the benefits of Ripple carry adder, Carry look-ahead adder and Carry select adder. Thus dividing the 32 bit number in to section of 8 bit each achieves multi precision addition. Hybrid multi precision adder is expected to achieve low propagation delay and high speed of operation