Design and Simulation of Advance Multi Precision Arithmetic Adder Using VHDL

Authors(3) :-Payal V. Mawale, Prof. Swapnil S. Jain, Prof. Pravin W. Jaronde

In the design of digital circuits using programmable logic array such as FPGA/CPLD low propagation delay, high speed & low area are the major parameter to be achieved. Digital circuits’ especially digital adders are implemented through three methods Ripple carry adder, Carry look-ahead adder and Carry select adder. Ripple carry adder suffers from high area and high propagation delay and high speed. Carry select adder incorporates pair of adder and select desired output sum and carry through multiplexers. Therefore carry look ahead adder suffers from high area requirements but achieving high speed of operations. Design of homogeneous single precision adder includes either ripple carry adder or carry look-ahead adder in combination with carry select adder in combines the advantages and disadvantages of both adders. It is proposed to design hybrid multi precision adder that includes Ripple carry adder, Carry look-ahead adder and Carry select adder. Hybrid adders combine the benefits of Ripple carry adder, Carry look-ahead adder and Carry select adder. Thus dividing the 32 bit number in to section of 8 bit each achieves multi precision addition. Hybrid multi precision adder is expected to achieve low propagation delay and high speed of operation

Authors and Affiliations

Payal V. Mawale
Department of Electronics and Telecommunication Engineering, DMIETR Wardha, Maharashtra, India
Prof. Swapnil S. Jain
Department of Electronics and telecommunication Engineering, DMIETR Wardha, Maharashtra, India
Prof. Pravin W. Jaronde
Department of Electronics and Telecommunication Engineering, DMIETR Wardha, Maharashtra, India

High Speed, Multi Precision, Low Area, Hybrid, Digital Adders

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Publication Details

Published in : Volume 4 | Issue 8 | May-June 2018
Date of Publication : 2018-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 578-583
Manuscript Number : IJSRSET1848163
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Payal V. Mawale, Prof. Swapnil S. Jain, Prof. Pravin W. Jaronde, " Design and Simulation of Advance Multi Precision Arithmetic Adder Using VHDL, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 8, pp.578-583, May-June-2018.
Journal URL : http://ijsrset.com/IJSRSET1848163

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