Leakage Current Reduction in CMOS Circuits Using Stacking Technique

Authors

  • N. Geetha Rani  Associate Professor, ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India
  • G. Ragapriya  ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India
  • Harshitha V  ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India
  • G. Swetha  ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India
  • B. Sri Jyothi  ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India

DOI:

https://doi.org//10.32628/IJSRSET207344

Keywords:

Low power, Power dissipation, Sub-threshold leakage current, Stacking effect, Cadence Virtuoso Tool.

Abstract

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2020-06-30

Issue

Volume 7, Issue 3, May-June-2020

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
N. Geetha Rani, G. Ragapriya, Harshitha V, G. Swetha, B. Sri Jyothi, " Leakage Current Reduction in CMOS Circuits Using Stacking Technique, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 7, Issue 3, pp.175-178, May-June-2020. Available at doi : https://doi.org/10.32628/IJSRSET207344