Robust 12T Sram Cell Using 45nm Technology
DOI:
https://doi.org//10.32628/IJSRSET207348Keywords:
SRAM, Micro wind Software, Power consumption, TransistorsAbstract
SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.
References
- Jinhui Chen Clark, L.T. Tai-Hua Chen, “An Ultra Low Power Memory with a Sub threshold Power Supply Voltage, Solid State Circuits, IEEE Journal, vol.41, Oct 2006, Issue: 10, pp- 2344-2353.
- Birla, Shilpi, et al., “Analysis of the data stability and leakage power in the various SRAM cells topologies,” ANALYSIS 2.7 (2010): 2936-2944.
- Priya, K. Gavaskar1 S, “Design Of Efficient Low Power 9t Sram Cell,” International Journal of Engineering 2.1 (2013).
- S.S.Rathod, S.Dasgupt, AshokSaxena, “Investigation of Stack as a Low Power Design Technique for 6-T SRAM cell,” Proc. IEEE TENCON, Nov.18-21, Univ.of Hyderabad, 2008, pp 1-5.
- Aly, R.E. Bayoumi, M.A., “Low-Power Cache Design Using 7T SRAM Cell,” Circuits and Systems II: Express Briefs, IEEE Transactions, vol. 54 April 2007, Issue: 4, pp. 318-322.
- Naveen Verma, Anantha P.Chandrakasan,“A 256kb 65nm 8T Subthreshold SRAM Employing Sense- Amplifier Redundancy,” Solid State Circuits, IEEE Journal, vol. 43, no. 1, Jan 2008, pp.141-150. [7]Liu, Zhiyu, andVolkanKursun, "Characterization of a novel nine-transistor SRAM cell," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 16.4 (2008): 488-492.
- Ghasem Pasandi1, Massoud Pedram1,“Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs,” IET Circuits, Devices & Systems, February 2, 2018.
- C. B. kushwah, S. K. vishvakarma, “a single-ended feedback control 8t sub threshold sramCell,”IEEE transactions on very large scale systems, January 17, 2016.
- Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam,“ Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell,” IEEE Transactions On Very Large Scale Systems, January 6, 2016.
- VivekaKonandurRajanna, Bharadwaj Amrutur, “A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide VoltageRange SRAMs,” IEEE Transactions on very Large Scale Systems, August 7, 2015.
- GhasemPasandi, Sied Mehdi Fakhraie, “ A 256- kb9T NearThreshold SRAM With 1k Cells per Bit line and Enhanced Write and Read Operations,” IEEE Transactions On Very Large Scale Systems, November 11, 2014.
Downloads
Published
Issue
Section
License
Copyright (c) IJSRSET
This work is licensed under a Creative Commons Attribution 4.0 International License.