A Survey on low power and memory efficient VLSI architecture for million bit multiplier Design

Abstract

The motto of this proposal is to design an area and memory efficient VLSI architecture for million bit multiplier design. The proposal work split the multiplier bit into 3FIFO architecture through NTT Ram technology. The final architecture include the Synchronizer, state control module as well as 3 state FIFO buffer module .The synchronizer module is used to synchronize the NTT RAM and state controller arbiter. The state controller module gives the control signal and priority of the multiplier design. The FIFO module is used for split the million bit multiplier into 8 bit multiplier i.e 256value.here we are going to design 3fifo module ,so we can achieve 256*256*256 bits of value aprx million bit, Based on this technology we have to achieve high speed as well as low power dissipation finally memory efficient vlsi architectures.