Four Quadrant Analog Multiplier Based on Squarer Cells
DOI:
https://doi.org/10.32628/IJSRSET1841078Keywords:
Analog Multiplier, Squarer Cell.Abstract
In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.
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2018-10-30
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How to Cite
[1]
Reza Zarei, Moora Maali "Four Quadrant Analog Multiplier Based on Squarer Cells" International Journal of Scientific Research in Science, Engineering and Technology (IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099,
Volume 4, Issue 10, pp.350-354, September-October-2018. Available at doi : https://doi.org/10.32628/IJSRSET1841078