Reversible Booth’s Multiplication Implementation using Reversible Gates

Abstract

One of the attractive research area in Engineering and Technology is Reversible Computing / Reversible logic. The attraction of scientists and researchers in this field in the last decade is strongly due to low-power consumption for the execution of operations. To minimize the width of circuit, garbage, total gate numbers and delay are the objectives of the reversible logic synthesis. This paper explains the design methodology regarding reversible Booth’s multiplier to be realized. Researchers’ attempts are thus making complete reversible logic circuits made up of reversible gates. Reversible Booth’s multiplication process as considered to be a speediest multiplier method. Being inspired in it, an efficient design-methodology for reversible paradigm is shown. The proposed architecture for reversible multiplication is capable of performing over signed and unsigned number multiplications for two input numbers without keeping any feedbacks. But the existing reversible mode of multiplication thinks of the feedback loop that is strongly prohibited in our present reversible multiplication mode. Theoretical underpinnings are able to show the efficiency of a reversible logic calculation and accordingly it is observed that our proposed circuit is more efficient with respect to the design viewpoint of a reversible circuit.