Minimization of Leakage Currents in Dram 4x4 Using SVL Technique
DOI:
https://doi.org//10.32628/IJSRSET218435Keywords:
Low Leakage Power, High Performance, Self-Controllable Voltage Level Technique, Low Cost, Low Power.Abstract
In recent years, due to development of integrated circuits technology, power is being given comparable weight to area and speed considerations. The power consumed for any given function in any complementary metal-oxide-semiconductor (CMOS) circuit must be reduced for either of the two different reasons. One is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an Integrated Circuit (IC) chip. Any amount of power dissipation is worthwhile as long as it does not degrade overall circuit performance. The other reason is to save energy in battery operated instruments like in electronic watches where average power is in microwatts. Low power is the major issue not only in portable devices but also in non-portable devices. So, it is apparent that one has to resolve low power design methodologies for the design of high throughput, low power digital systems. By using this SVL technique using DRAM we are going to reduce the leakage currents and also improves the performance of the circuit.
References
- Frangois Odiot, Hugues dry, “New check Structure for prime Resozution discharge Current And Capacitance Measurements In CMOS Imager Appncations,” Proc. 1EEE 2004 Int. Conference On electronics check Structures, Vol 15, March 2004.
- Satoshi Kurihara, Yanuar Z. Arief, Takumi Tsurusaki, Shinya Ohtsuka, “Construction Of Remote watching System For Separative measure Of discharge Current Of Out door Insulators,” Proceedings Of The fifth Lntemarional Confere.
- Sandeep K. Shukla, R. Iris Bahar (2004). Nano, Quantum and Molecular Computing. Springer, p. 10 and Fig. 1.4, p. 11
- Ashish Srivastava, Dennis Sylvester, David Blaauw (2005).Statistical Analysis and improvement For VLSI: temporal order and Power. Springer, p. 135
- Galup-Montoro & Schneider megacycle (2007).MOSFET modeling for circuit analysis and style. London/Singapore: World Scientific, p. 83
- Norbert R leader (1995).Electronic circuits: analysis, simulation, and design. Englewood Cliffs, NJ : Prentice Hall, pp. 315-316
- A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume producing logic technology that includes novel 45nm gate length strained semiconducting material CMOS transistors,” IEDM Technical Digest, pp. 978-980, 2003.
- K. Bowman, L. Wang, X. Tang, and J. Meindl, “A circuit-level perspective of the optimum gate chemical compound thickness,” IEEE Trans. lepton Devices, vol. 48, no. 8, pp. 1800–1810, Aug. 2001.
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