A Power-Efficient FPGA Test Pattern Composer
Keywords:
LUT, SRAM, Von-Neumann Corrector, True-Random Number Generator, Clock gating, Xilinx, Random JitterAbstract
The paper presents a novel approach to generating true random number sequences in Xilinx hardware using the random jitter of free-running oscillators. By employing programmable delay lines, the proposed method aims to reduce correlation between oscillator rings, enhancing randomness. Post- processing techniques such as Von-Neumann correction are applied to refine the generated sequences. Additionally, clock gating architecture is utilized to improve power efficiency by reducing switching activity. Notably, the design omits data and read/write lines in SRAM memory architecture due to LUT memory accessing not requiring write operations.
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