Hybrid Full Adder Circuit Utilizing Pass Transistor Logic and PFAL Logic
Keywords:
Low Power VLSI, Adiabatic Logic, Pass Transistor Logic, Full Adder, Engineering, TechnologyAbstract
This paper presents a comprehensive design and analysis of a hybrid full adder circuit that integrates XOR gates and 2:1 multiplexers utilizing pass transistor logic, combined with PFAL (Pulsed-Fully Adiabatic Logic) adiabatic logic style. The primary objective is to enhance the performance and power efficiency of arithmetic operations in digital circuits. The proposed hybrid full adder leverages the strengths of XOR gates and multiplexers to achieve high-speed and low-power operation. The use of pass transistor logic in the design improves circuit efficiency by reducing power consumption compared to traditional static CMOS logic. The PFAL adiabatic logic style further contributes to power savings by minimizing energy dissipation during the switching process, thus making it well-suited for energy-constrained applications.
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