K. PASIPALANA RAO; CH. HARI CHANDRIKA; G. RAMYA KRISHNA; G. ANITHA ISWARYA. A Power-Efficient FPGA Test Pattern Composer. International Journal of Scientific Research in Science, Engineering and Technology, [S. l.], v. 11, n. 2, p. 333–341, 2024. Disponível em: https://ijsrset.com/index.php/home/article/view/IJSRSET2411250.. Acesso em: 18 may. 2024.