Simulation and Analysis of Inverting and Non-Inverting Mixed Logic 2 To 4 Decoder Using 32 Nanometer Fin-FET Technology
DOI:
https://doi.org/10.32628/IJSRSET25122188Keywords:
low power, low area, high efficient, 32nm Fin-FETAbstract
Because it is difficult to work with low-power devices for higher-ranking applications (such as microprocessors, DSPs, and SRAMs), this project emphasizes the need for applications that use less power yet have better performance. The Decoder's key role in memory and logical circuit design is well knowledge. According to the recommendations made for 32nm technology, I have been studying the specifications of 12T and 14T decoders based on MOS, Fin-FET, and MTCMOS, including latency, power consumption, and the power delay product. The suggested circuit may be improved as required by changing the ground path of the final 12T using MTCMOS.
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